EDN

RTL test objects at ITC

Testability strategies able to handle 65-nm and denser processes highlighted EDA firms’ presentations at last week’s International Test Conference. In particular, power-aware and small-delay-defect ...
EDN

Take scan test out of the critical path

Integrated circuit complexity and integration continuously advances, posing challenges to the development process. Market profitability, however, demands that products be designed and produced as fast ...
Electronic Design

TetraMAX II shortens test pattern generation from days to hours

Mountain View, CA. Synopsys Inc. on Tuesday announced its next-generation ATPG and diagnostics solution, TetraMAX II, incorporating the innovative test engines unveiled at the International Test ...
Electronic Design

Design-For-Test Links Design And Manufacturing

Historically, testability is an afterthought in the design process. But heightening complexity of chip designs, and especially SoCs, forces testability (and manufacturability) to take a more central ...
Semiconductor Engineering

Smart Plug-And-Play DFT For Arm Cores

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ...
Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
Semiconductor Engineering

Balancing Power And Test

The International Test Conference will be held at the Disneyland resort hotel in Anaheim, Calif., from Nov. 4-9. One of the biggest concerns for the test engineering community is to account for the ...